The present disclosure relates to digital phase locked loops.
A phase locked loop (PLL) circuit can be used to generate signals with a range of frequencies from a clean reference clock source. In some applications, a fast phase locking over a wide frequency range is desired to improve time utilization. An example of such an application is a disk drive storage device with a PLL circuit that may be required to settle within 100 to 200 nanoseconds for a frequency change as high as 15%. Such a fast settling requirement may translate to increased PLL bandwidth (e.g., in the order of tens of megahertz) and phase margin for optimum settling characteristics. However, a PLL circuit with a high bandwidth may be difficult to implement and may exhibit poor performance.